1-MHz linewidth VCSEL enabled by monolithically integrated passive cavity for high-stability chip-scale atomic clocks

Zhiting Tang; Chuanlin Li; Xuhao Zhang; Wuyang Ren; Kai Shen; Chuang Li; Qingsong Bai; Jin Li; Aobo Ren; Hao Wang; Xiaorong Luo; Hongxing Xu; Jiang Wu

doi:10.1038/s41377-026-02192-x

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1-MHz linewidth VCSEL enabled by monolithically integrated passive cavity for high-stability chip-scale atomic clocks

Original Articles

- 1-MHz linewidth VCSEL enabled by monolithically integrated passive cavity for high-stability chip-scale atomic clocks
- Light: Science & Applications Vol. 15, Issue 4, Pages: 1105-1115(2026)
- Affiliations：
  
  1.Institute of Fundamental and Frontier Sciences, University of Electronic Science and Technology of China, Chengdu 611731, China
  2.Chengdu Spaceon Electronics Corporation Ltd., Chengdu 610036, China
  3.School of Instrumentation and Optoelectronic Engineering, Beihang University, 100191 Beijing, China
  4.Division of Electrical Engineering, Department of Engineering, University of Cambridge, Cambridge CB3 0FA, UK
  5.College of Microelectronics, Chengdu University of Information Technology, Chengdu, China
  6.State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 611731, China
  7.Mozi Laboratory, Zhengzhou 450001, China
- Author bio：
  
  Aobo Ren (aobo.ren@uestc.edu.cn)
  Hao Wang (hw447@cam.ac.uk)
  Jiang Wu (jiangwu@uestc.edu.cn)
- Funds：
- DOI：10.1038/s41377-026-02192-x
  CLC：
- Received：13 October 2025，
  
  Revised：2025-12-29，
  
  Accepted：12 January 2026，
  
  Online First：29 January 2026，
  
  Published：30 April 2026
- Accepted：
Scan QR Code
Tang, Z. T. et al. 1-MHz linewidth VCSEL enabled by monolithically integrated passive cavity for high-stability chip-scale atomic clocks. Light: Science & Applications, 15, 1105-1115 (2026).
DOI：

Tang, Z. T. et al. 1-MHz linewidth VCSEL enabled by monolithically integrated passive cavity for high-stability chip-scale atomic clocks. Light: Science & Applications, 15, 1105-1115 (2026). DOI： 10.1038/s41377-026-02192-x.

摘要

Abstract

Narrow-linewidth vertical-cavity surface-emitting lasers (VCSELs) are key enablers for chip-scale atomic

clocks and quantum sensors

yet conventional designs suffer from short cavity lengths and excess spontaneous emission

resulting in broad linewidths and degraded frequency stability. Here

we demonstrate a monolithically integrated VCSEL operating at the cesium D

line (894.6 nm) that achieves intrinsic linewidth compression to ~1 MHz

without requiring external optical feedback. This performance is enabled by embedding a passive cavity adjacent to the active region

which spatially redistributes the optical field into a low-loss region

extending photon lifetime while suppressing higher-order transverse and longitudinal modes. The resulting device exhibits robust single-mode operation over a wide current and temperature range

with side-mode suppression ratio (SMSR)

35 dB

orthogonal polarization suppression ratio (OPSR)

25 dB and a beam divergence of ~7°. Integrated into a Cesium vapor-cell atomic clock

the VCSEL supports a frequency stability of 1.89 × 10

–12

-1/2

. These results position this VCSEL architecture as a compact

scalable solution for next-generation quantum-enabled frequency references and sensing platforms.

关键词

Keywords

references

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